Hardware Archives - RISC-V International
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RISC-V provides an open foundation for hardware design, enabling custom processors, accelerators, and systems without restrictive licensing. This tag is for original stories that explore the latest RISC-V hardware, from dev boards to data centers.
Mar
24
Using a Performance Model to Implement a Superscalar CVA6
By
RISC-V International Staff
Featured Work
Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6 RISC-V processor, built to evaluate…
Jan
27
How We’re Using AI to Streamline RISC-V Regression Debugging
By
RISC-V International Staff
Featured Work
AI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
Dec
10
Ocelot3: Full Vector “V” Extension for BOOM
By
RISC-V International Staff
Featured Work
Project Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The decoupled VPU is connected through…
Oct
16
Optimizing Hardware for Neural Network Inference using Virtual Prototypes
By
RISC-V International Staff
Featured Work
Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications significantly increases resource utilization. We…
Oct
09
Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
By
Anisha Sharma
News and Updates
The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process, represents a leap forward in…
Aug
26
CVA6 RISC-V PMP Vulnerabilities against FIA
By
RISC-V International Staff
Featured Work
Project Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering its clock signal, power supply…
Jul
29
Learning Computer Architecture with a Visual Simulation of RISC-V Processors
By
RISC-V International Staff
Featured Work
Project Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs. Enhancements to Logisim Evolution allow…
Jun
24
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography
By
RISC-V International Staff
Featured Work
Project Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the fourth round of PQC standardization.…
May
30
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
By
RISC-V International Staff
Featured Work
Project Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed and taught…
Feb
18
TestRIG – Randomized Testing of RISC-V CPUs
By
RISC-V International Staff
Featured Work
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a…
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