LATTE '21

LATTE '21
LATTE '21 has concluded.
Please feel free to participate in the
discussion threads
for
the various papers and other topics.
Hope to see you next year!
LATTE is an
ASPLOS
workshop on applying programming languages and compilers
techniques to generate hardware accelerators.
The workshop will take place on
April 15, 2021
and will feature 23 papers
along with 2 keynote presentations.
The
call for participation
has been archived.
Read
Rachit's blog post
summarizing the work in this area and advertising the workshop.
Please register for it through the
ASPLOS registration website
Program
The LATTE program will consist of sessions of 2-3 papers each grouped according
to their theme.
Each paper talk will be 6 minutes long and prerecorded.
After the talk, we will spend 6 minutes in small breakout rooms discussion the
session papers.
After that, we will regroup in the main session and dedicate 6 minutes for
plenary questions to the authors.
All talks will be released a few days before the workshop.
To enable extensive discussions, each paper will have
Github discussion
thread
Authors will be subscribed to the thread for their paper and will answer questions
during and (hopefully) after the workshop!
Time (EST)
Event
10am - 10.15am
Opening & Introductions
10.15am - 11am
Keynote - Sharad Malik
11am - 11.30am
Session 1 - Formal
11.30am - 12pm
Session 2 - Language Design
12pm - 12.15pm
Break
12.15pm - 12.45pm
Session 3 - HDL
12.45pm - 1.15pm
Session 4 - Interconnect & Memory
1.15pm - 2.00pm
Lunch Break
2.00pm - 2.30pm
Topic Discussion
2.30pm - 3.00pm
Session 5 - Integration
3.00pm - 3.45pm
Keynote - Sophia Yakun Shao
3.45pm - 4.15pm
Session 6 - HLS
4.15pm - 4.30pm
Break
4.30pm - 5pm
Session 7 - Industrial & Applications
5pm - 5.30
Session 8 - Abstractions
5.30pm - 6pm
Closing Discussion
Discussion Topics
We will have 1-2 short discussion sessions that will feature a debate
among the attendees.
We need your help building a list of controversial topics to serve as grist for
the discussion mill.
Please submit a sentence or two about an open problem, philosophical question,
or other thought you'd like to see discussed at the workshop.
You can submit as many of these as you like.
We'll use these suggestions to set up a debate during the workshop.
Add your topic suggestions by editing
this wiki page
on GitHub.
Keynotes
Sharad Malik
Hardware-Software Interface Specification for Verification in Accelerator-Rich Platforms
Yakun Sophia Shao
: Efficient and Productive: Holistic Approach to Accelerator Design, Integration, and Scheduling
Accepted Papers
The LATTE 21 program will feature the following 23 papers and will be discussed
using
SNAPL
's round-table discussion format.
Papers are grouped based on a theme.
Each session will start with all papers of a theme and follow with the
discussions.
The camera-ready version for each paper is linked here.
A few days before the workshop, we will link the prerecorded talks for each
paper as well as the
Github discussion
for each paper.
Abstractions
A Position on Transparent Reconfigurable Systems
Luís Sousa (Faculty of Engineering, University of Porto); Nuno Paulino and João Canas Ferreira (INESC-TEC and Faculty of Engineering, University of Porto)
Thread
Talk
Generality is the Key Dimension in Accelerator Design
Jian Weng, Vidushi Dadu, Sihao Liu, and Tony Nowatzki (UCLA)
Thread
Talk
Formal
High-Level Synthesis Tools should be Proven Correct
Yann Herklotz and John Wickerson (Imperial College London)
Thread
Talk
What are the Semantics of Hardware?
Gilbert Bernstein (Berkeley); Ross Daly (Stanford); Jonathan Ragan-Kelley (MIT); Pat Hanrahan (Stanford)
Thread
Talk
HDL
Registerless Hardware Description
Oron Port and Yoav Etsion (Technion - Israel Institute of Technology)
Thread
Talk
Compile-Time RTL Interpreters
Sahand Kashani and James R. Larus (EPFL)
Thread
Talk
Design Decisions in LiveHD for HDLs Compilation
Sheng-Hong Wang and Jose Renau (University of California - Santa Cruz)
Thread
Talk
HLS
ScaleHLS: Achieving Scalable High-Level Synthesis through MLIR
Hanchen Ye (University of Illinois at Urbana-Champaign); Cong Hao (Georgia Institute of Technology); Hyunmin Jeong, Jack Huang, and Deming Chen (University of Illinois at Urbana-Champaign)
Thread
Talk
Improving HLS with Shared Accelerators: A Retrospective
Parnian Mokri and Mark Hempstead (Tufts University)
Thread
Talk
High-Level Synthesis of Security Properties via Software-Level Abstractions
Christian Pilato (Politecnico di Milano); Francesco Regazzoni (Università della Svizzera italiana)
Thread
Talk
Industrial & Applications
Enabling Cross-Domain Communication: How to Bridge the Gap between AI and HW Engineers
Michael J. Klaiber, Axel J. Acosta, Ingo Feldner, and Falk Rehm (Robert Bosch GmbH)
Thread
Talk
Building Beyond HLS: Graph Analysis and Others
Pedro Filipe Silva (Faculty of Engineering, University of Porto); João Bispo and Nuno Paulino (INESC-TEC and Faculty of Engineering, University of Porto)
Thread
Talk
Faster Coverage Convergence with Automatic Test ParameterTuning in Constrained Random Verification
Qijing Huang (Google; UC Berkeley); Hamid Shojaei, Fred Zyda, and Azade Nazi (Google); Shobha Vasudevan (Google; UIUC); Sat Chatterjee and Richard Ho (Google)
Thread
Talk
Integration
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation
Andre DeHon, Hans Giesen, Nik Sultana, and Yuanlong Xiao (University of Pennsylvania)
Thread
Talk
Single-Source Hardware-Software Codesign
Blaise Tine, Hyesoon Kim, and Sudhakar Yalamanchili (Georgia Institute of Technology)
Thread
Talk
(Redacted)
(Redacted)
Interconnect & Memory
Elastic Silicon Interconnects: Abstracting Communication in Accelerator Design
John Demme (Microsoft)
Thread
Talk
Compiler Infrastructure for Specializing Domain-Specific Memory Templates
Stephanie Soldavini and Christian Pilato (Politecnico di Milano)
Thread
Talk
The Enzian Coherent Interconnect (ECI): Opening a coherence protocol to research and applications
Abishek Ramdas, David Cock, Timothy Roscoe, and Gustavo Alonso (ETH Zurich)
Thread
Talk
Language Design
Phism: Polyhedral High-Level Synthesis in MLIR
Ruizhe Zhao and Jianyi Cheng (Imperial College London)
Thread
Talk
Towards Higher-Level Synthesis and Co-design with Python
Alexandre Quenon and Vitor Ramos Gomes da Silva (University of Mons)
Thread
Talk
Application specific dataflow machine construction for programming FPGAs via Lucent
Nick Brown (EPCC at the University of Edinburgh)
Thread
Talk
Program Committee
Thomas Bourgeat, MIT
Ross Daly, Stanford
David Durst
, Stanford
Tobias Grosser, ETH Zürich
Shunning Jiang, Cornell
Lana Josipović, EPFL
Vinod Kathail, Xilinx
Chris Leary, Google
Thierry Moreau, OctoML
Clément Pit-Claudel
, MIT
Jose Renau, UCSC
Hongbo Rong, Intel
John Wickerson, ICL
Organizing Committee
Rachit Nigam
, Cornell University
Adrian Sampson
, Cornell University
Stephen Neuendorffer, Xilinx
Zhiru Zhang
, Cornell University