Technical Steering Committee - RISC-V International

Technical Steering Committee - RISC-V International
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Technical Steering Committee
The Technical Steering Committee guides technical direction, ensuring high-quality specifications and fostering RISC-V community engagement.
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The Technical Steering Committee (TSC) is the technical governing body that includes all representatives from TSC-level member organizations and community elected TSC representatives (2 from the Strategic and 1 from the Community/Individual members).
Officers
Greg Favor
Qualcomm
TSC Chair
Greg Favor
Greg is Co-Founder and CTO of Ventana Micro Systems.
Philipp Tomsich
VRULL GmbH
TSC Vice-Chair
Philipp Tomsich
Dr. Philipp Tomsich is Chief Technologist and Founder of VRULL, a company providing outsourced R&D for semiconductor companies: services range from tools for pre-silicon architectural exploration to the building of software ecosystems .
As a delegate for VRULL, he supports RISC-V International as the Vice Chair of the Technical Steering Committee and as the Chair of the Applications and tools Horizontal Committee.
In these roles, he oversees the software ecosystem outreach, software-derived standardisation, and the efforts to optimise for established and emerging application domains (such as AI/ML).
Philipp also serves on the Board of Directors of RISC-V, continuing to drive the empowerment of the software ecosystem perspective within RISC-V and to make it the premier platform for software innovation. During his tenure on the Board, he advocated for a closer alignment with international standards bodies, such as ISO JTC1, to further strengthen RISC-V as a global standard and to reinforce global collaboration.
Philipp is a guest professor of computer architecture at the University of Tirana. Previously, Philipp held teaching and research roles at the Vienna University of Technology, worked as compiler engineer at Silicon Graphics Inc., consulted in banking and government IT, and went on to build and exit Theobroma Systems (recently renamed Cherry Embedded Solutions).
Philipp holds a Master’s Degree and a Doctorate Degree in Computer Science from the Technical University of Vienna.
For his contributions at RISC-V, Philipp has been awarded the 2021 RISC-V Community Contributor Award and the 2021 RISC-V Board of Directors Technical Leadership Award.
Philipp is a recurring invited speaker at international conferences around the world, where he shares his insights on the pivotal role of software engineering in the future of silicon and AI.
Members
Avi Timor
Google
Premier
Avi Timor
Avi works in CPU Architecture and Design at Google.
Charlie Su
Andes Technology Corporation
Premier
Charlie Su
Charlie is CTO and President at Andes Technology Corporation.
David Chen
Stream Computing
Premier
David Chen
Dr. David Chen, Executive Vice President at Stream Computing, responsible for building ecosystem, business development and global partnership to promote RISC-V in AI area.
He is also the vice chair of Application and Tools HC in RISC-V International as well as the vice chair of AI/ML SIG. In the past 4 years, he worked closely within this HC to successfully incubated and operated dozens of groups under TSC including Android SIG, RVM-CSI SIG, AME TG, AI/ML SIG etc.
Before that David was the Director of Ecosystem at Alibaba DAMO Academy, the Director of Arm education program in APAC and then China, his interests are academic projects on embedded systems, IOT, and AI technology. David also has professional positions in several top universities in China. He received his MS and PhD degrees in Mechanical Engineering from Michigan Technological University.
David Weaver
Akeana
Premier
David Weaver
In Dave’s early career, he led a team developing software cross-development tools for embedded processors.  He became as ISA Architect for another UCB RISC-derived architecture (SPARC), where he was responsible for architectural consistency, architecture specifications, opcode space management, and coordination of all ISA extensions for 20+ yrs.  That work required collaboration across many technical disciplines (and multiple companies).  He served for 7 years as a Director on the Board of SPARC International (similar to RISC-V International).  After that, he worked in Architecture Research at Arm for a few years.  He currently serves as a Principal Architect at Akeana and participates in numerous RISC-V SIGs and technical Task Groups.
Derek Zhang
Huawei
Premier
Derek Zhang
Derek Zhang is the Director of RISC-V Standardization & Industry Dept in Huawei. He is specializing in leading RISC-V resources across both hardware design and software solutions and responsible for driving strategic initiatives aimed at expanding in various verticals, including Consumer Electronics, Smart Home, and Automotive, through innovative solutions.
Earl Killian
Aril Inc
Unpriv IC
Earl Killian
Earl is CTO of Aril Inc. In his career he has worked as a software engineer (operating systems, compilers, and networking) and microprocessor architect. He graduated from MIT in 1978 (B.S. Electrical Engineering and Computer Science), first working on software at BBN and LLNL, and subsequently in software and microprocessor design at MIPS, QED, SGI, and Tensilica, all silicon valley companies engaged in creating microprocessor products for both general-purpose and embedded computing as well as some experience in HPC. Earl was a co-founder and CTO of QED, and held the title Director of Architecture at each of the other companies. His microprocessor work has resulted in 34 patents issued so far. He has been involved in the specification of several Instruction Set Architectures.
Erich Focht
OpenChip
Premier
Erich Focht
Erich is working as Fellow at OpenChip, doing hardware, system and software architecture. He has a PhD in theoretical physics from RWTH Aachen and has worked in computational physics, numeric algorithms research, distributed systems, Linux kernel development, system, software and hardware architecture R&D at NEC HPC Europe. He is a long time vector computing advocate and excited about the democratization of computer hardware through RISC-V.
Frans Sijstermans
NVIDIA
Premier
Frans Sijstermans
Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.
Guido Araujo
Ministry of Science, Technology and Innovation (Brazil)
Premier
Guido Araujo
Full Professor of Computer Science and Engineering at the University of Campinas (UNICAMP). Member of the technical advisory board of Eldorado and SIDI R&D Institutes and the CI-Brasil Council at the Brazilian Ministry of Science and Technology. Co-founded companies Kryptus and Idea! and is a member of the Editorial Board of IEEE MICRO. His current interests include code optimization, parallelizing compilers, and compiling for accelerators targeting RISC-V, which are explored in close cooperation with industrial partners.
Guohua Chen
ESWIN Computing
Premier
Guohua Chen
As head of RISC-V core development at ESWIN Computing, I drive the design and implementation of cutting-edge RISC-V processors architectures and lead cross-fuction teams to deliver scalable, customizeable RISC-V IP cores for diverse applications, including AIoT, automotive, and edge computing.
Guy Lemieux
Individual Member
Community Representative
Guy Lemieux
Guy has been a Professor in Computer Engineering at the University of British Columbia for over 20 years where I teach advanced digital design and computer systems/architecture related courses. My undergrad and graduate degrees are all from the University of Toronto. I’ve built processors from scratch (RISC-V and others), co-founded VectorBlox Computing where we developed the MXP (Matrix Processor) as a vector accelerator for RISC-V and other ISAs. In grad school, I co-designed custom designed cache-coherent multiprocessors that were built from MIPS R4400 CPUs and custom PCBs and FPGA circuitry. My research focuses on improving FPGA devices and CAD tools, in particular making them easier to use for computing tasks. I was a member of the RISC-V Vector Committee and the early Cache Management Operations committee, and I chair the RISC-V SoftCPU SIG. I’ve also given several talks at RISC-V meetings.
Hongbin Zhang
Institute of Software, Chinese Academy of Sciences
Premier
Hongbin Zhang
Hongbin Zhang
is a postdoctoral researcher at the Institute of Software, Chinese Academy of Sciences. He received his Ph.D. degree from the University of Chinese Academy of Sciences. His research focuses on compiler technology and software-hardware co-design techniques. As an MLIR contributor, he is actively exploring the integration between the MLIR framework and the RISC-V ecosystem.
Jian Zhang
Beijing Institute of Open Source Chip
Premier
Jian Zhang
Jian Zhang is a Product Manager at BOSC, specializing in high-performance computing IP, including CPU, NoC and others. Prior to joining BOSC, Jian accumulated over 15 years of experience as a software engineer, working extensively in operating systems for both server and embedded systems. His deep expertise in software and hardware integration.
Jianlin Gao
Tencent
Premier
Jianlin Gao
Jianlin Gao is the Director of panglai laboratory in Tencent . He is a expert in IC and OS software, developed the edge AI chip“penglai” and cloud side AI chip “zixiao” as main architect , also designed the codec chip “canghai”, support H265 and H266 encode.
Kan Shi
Chinese Academy of Sciences
Premier
Kan Shi
Dr. Kan Shi is currently an Associate Professor at the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include agile chip design, reconfigurable computing, and cloud data center architecture.
Dr. Shi earned his PhD from Imperial College London, and then worked at Intel UK R&D center as an SoC Design Engineer, with focus on developing FPGA-based SmartNIC/DPU/IPU and their applications in cloud data centers.
Ken Dockser
Tenstorrent
Premier
Ken Dockser
Ken continues to be passionate about RISC-V and all of its potential!
Since 2018 he has actively contributed to the RISC-V community through serving on the Board of Directors and the Technical Steering Committee, heading several Task Groups, authoring several ISA extensions, contributing to many TGs & SIGs, and making multiple presentations at RISC-V Summits and Workshops. In his day job, he has played a key role in the development and optimization of several RISC-V implementations.
Ken is a Senior Principal Architect at Tenstorrent where he defines high-end RISC-V processors and systems.
Ken has over 37 years of experience in computer architecture and development, and has over three dozen patents.
When not helping develop the RISC-V architecture, implementing RISC-V designs, helping develop new floating point standards (IEEE P3109 and IEEE-754), or developing processor benchmarks (SPEC OSG), Ken can be found spending time with family, fiddling with antique phonographs, and playing classical guitar.
Krste Asanović
SiFive
Premier
Krste Asanović
Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-­V ISA project at UC Berkeley, serves as chairman of RISC-V International, and co­founded SiFive Inc. to support commercial use of RISC­-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.
Manu Gulati
Qualcomm
Premier
Manu Gulati
Manu Gulati is currently VP at Qualcomm, where he performs both engineering and business development functions. A product of Indian Institute of Technology Delhi and UC Irvine, Manu has been closely involved in the design, tapeout and production of chips ranging from the largest high-performing server SOCs,  to small purpose-built ones for embedded applications over the last 30 years.
Manu served as SOC architect for mobile phone chips at Apple and Google for 10 years before co-founding his own startup called Nuvia in 2019, creating CPUs and SOCs for the server market. Nuvia was acquired by Qualcomm in 2021. This experience has given Manu a blend of hardware, system and software background crucial to taking products to market successfully.
Marcel Tromp
Infineon Technologies
Premier
Marcel Tromp
Marcel Tromp is a Fellow at Infineon Technologies where he drives platform architectures and methodologies as well as processor strategy, including RISC-V adoption.
Marcel started his career at Philips Research as a VLIW CPU architect and later served as chief architect at TriMedia and Equator Technologies. He has held both senior technical and managerial roles defining and delivering complex SoC’s at LSI Logic, Magnum Semiconductor and Cypress Semiconductor.
Marcel holds a MSc. in Electrical Engineering from the University of Twente in the Netherlands.
Nambi Ju
Individual Member
Chair of Tech HC
Nambi Ju
Paul Holt
Synopsys
Premier
Paul Holt
Paul is VP R&D ARC Processor IP at Synopsys.
Shi Yijun
Sanechips/ZTE
Premier
Shi Yijun
Shi is at Sanechips/ZTE.
Siqi Zhao
Alibaba DAMO Academy
Premier
Siqi Zhao
Siqi is a Technology Expert of the CPU R&D Department in Alibaba DAMO Academy. His current job focuses on the security and related architecture of the Xuantie processors, with an emphasis on the collaboration with and contribution to the open RISC-V community.   He is currently serving as the chair of the Unified Discovery TG, and has contributed to a number of specifications including proposals for the IOMMU and memory tagging.
Tariq Kurd
Codasip
Strategic Representative
Tariq Kurd
Tariq
is the Chief Architect and a Distinguished Engineer at Codasip. He has 30 years experience in the silicon industry, and has worked for major companies such as NVIDIA, Broadcom, Huawei and STMicroelectronics. He is an active participant in the RISC-V standard body, having ratified multiple RISC-V extensions. He has spend 4 years working on CHERI and aims to bring memory safety to mainstream computing.
Tom Zhao
Phytium
Premier
Tom Zhao
Tom is a Technical Expert at Phytium.
Wei Wu
ISCAS
Chair of ISA Infra HC
Wei Wu
Wei Wu is the Co-Founder and VP of Products at KUBUDS, which is a tech startup focusing on fundamental software and RISC-V ecosystem. Before
KUBUDS, he founded the PLCT Lab, which had become a well-known contributor to the RISC-V ecosystem. He serves as the Chair of the RISC-V Infra HC. He is also a RISC-V Ambassador.
Zhangxi Tan
RIOS Laboratory
Premier
Zhangxi Tan
Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.
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